Profile Research I have worked on the CodeGen, Scheduling and Register Allocation on the LLVM Compiler Framework Currently looking at the Galois parallelization model which looks at exploiting speculative execution for Data-Parallel algorithms Professional Experience (Feb 2013- Dec 2013) – R.R. Logic Systems. (July 2011- Feb 2013) – Cisco Systems India Pvt. Ltd. Education M.S (Jan 2014- Present) from Indian Institute of Technology, Madras under Computer Science and Engineering department. B.E (2007- 2011) from Sri Jayachamarajendra College of Engineering with cumulative GPA of 8.79 under Computer Science and Engineering department.